ASPLOS 2015 @Istanbul

Conference

VEE 2015 - 11th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environment

Workshop date: Sunday, March 15, 2015
Duration: Half day (Afternoon)
Location: Pinar3
Abstract: The Intel® Edison development platform is the first in a series of low-cost, product-ready, general purpose compute platforms that help lower the barriers to entry for entrepreneurs of all sizes from pro makers to consumer electronics and companies working in the Internet of Things (IoT).
Edison
Agenda
- Introduction to Internet of things (opportunities)
- Edison Overview
- Edison Architecture
- Edison Release 1 Software Stack
- Shield pin GPIO mapping
- Edison Developer options(Cloud, IDE, Programming languages, OS Boot Images, Tools and Libraries)
- Hands on development session on Edison board

Sirius Tutorial
Presenters: Jason Mars, University of Michigan and Lingjia Tang, University of Michigan
Tutorial date: Saturday, March 14, 2015
Duration: Half day (Morning)
Location: Esen1
Abstract: As user demand scales for intelligent personal assistants (IPAs) such as Apple’s Siri, Google’s Google Now, and Microsoft’s Cortana, we are approaching the computational limits of current datacenter system architectures. It is an open question how future server architectures should evolve to enable this emerging class of applications, and the lack of an open representative workload is an obstacle in addressing these questions. In this tutorial, we present the design of Sirius, an open end-to-end IPA web service application that accepts queries in the form of voice and images, and responds with natural language. We then show how this workload can be used to investigate the implications of ?ve points in the design space of future accelerator-based server architectures spanning GPUs, manycore throughput coprocessors such as Intel Phi, and FPGAs. To investigate future server designs for Sirius, we decompose Sirius into a suite of 7 benchmarks (Sirius Suite) comprising the computationally intensive bottlenecks of Sirius. We port Sirius Suite to our ?ve accelerator platforms and use the performance and power trade-offs across these platforms to perform a total cost of ownership (TCO) analysis of various server design points.

DataFlow Tutorial
Presenter: Veljko Milutinovic, University of Belgrade
Tutorial date: Saturday, March 14, 2015
Duration: Half day (Afternoon)
Location: Esen1
Abstract: This tutorial analyses the essence of DataFlow SuperComputing, defines its advantages and sheds light on the related programming model for energy-aware programming, based on the new OpenSPL and WebIDE environments. DataFlow computers, compared to ControlFlow computers, offer speedups of 20 to 200 (even 2000 for some applications), power reductions of about 20, and size reductions of also about 20. However, the programming paradigm is different. The later part of the tutorial explains the paradigm, using Maxeler as an example and sheds light on the ongoing research in the field. Examples include GeoPhysics, SignalProcessing, DataMining, FinancialEngineering, etc...

Non-Volatile Memory Tutorial
Presenters: Michael M. Swift, University of Wisconsin, Haris Volos, HP
Tutorial date: Saturday, March 14, 2015
Duration: Half day (Afternoon)
Location: Esen2
Abstract: Non-volatile memory (NVM) technologies, such as phase-change memory, memristors, spin-transfer torque MRAM, and others promise high-bandwidth, low-latency persistent storage through the standard memory interface. However, making memory persistent poses a number of challenges, including how to ensure data is durable in the presence of processor caches, and how to ensure consistency of updates. This tutorial will briefly survey NVM technologies, and then cover (i) usage models, such as file systems and persistent memory (ii), programming models, such as NV-Heaps and Mnemosyne’s persistent heaps, and (iii) consistency and durability mechanisms.

Hardware Security Tutorial
Presenters: Ruby Lee (Princeton), Robert Aitkins (ARM), David Kaplan (AMD) and Shay Gueron (Intel)
Tutorial date: Sunday, March 15, 2015
Duration: Full day
Location: Esen1
Abstract: Security is now an essential part of all computer systems designs, from IoT devices and smartphones to cloud computing servers. This Hardware Security tutorial will give a very quick tutorial on fundamental security concepts, followed by eminent industry security experts from ARM, AMD and Intel speaking on important threats tackled by industry and the security hardware-related architectures and mechanisms used or proposed. A brief survey of academic research in hardware security will also be given, time permitting. The presenters, as a panel, will also field questions at the end.

Big Data Tutorial
Presenters: Dhabaleswar K. Panda, Ohio State University and Xiaoyi Lu, Ohio State University
Tutorial date: Sunday, March 15, 2015
Duration: Half day (Afternoon)
Location: Esen2
Apache Hadoop and Spark are gaining prominence in handling Big Data and analytics. Similarly, Memcached in Web 2.0 environment is becoming important for large-scale query processing. These middleware are traditionally written with sockets and do not deliver best performance on datacenters with modern high performance networks. In this tutorial, we will provide an in-depth overview of the architecture of Hadoop components (HDFS, MapReduce, RPC, HBase, etc.), Spark and Memcached. We will examine the challenges in re-designing the networking and I/O components of these middleware with modern interconnects, protocols (such as In?niBand, iWARP, RoCE, and RSocket) with RDMA and storage architecture. Using the publicly available software packages in the High-Performance Big Data (HiBD, http://hibd.cse.ohio-state.edu) project, we will provide case studies of the new designs for several Hadoop/Spark/Memcached components and their associated bene?ts. Through these case studies, we will also examine the interplay between high performance interconnects, storage systems (HDD and SSD), and multi-core platforms to achieve the best solutions for these components.